One approach to increasing performance of embedded logics is to add a significant amount of pipelining in programmable elements, for instance, by making every lookup table (LUT) latched. This is generally also prohibitive, for two reasons:
- It increases the latency, as each LUT will now take a whole clock cycle to compute.
- Power dissipation increases dramatically, since each latch draws power even if the data does not change.
Technologies
The proposed Pipelined Logic architecture uses a self-timed, ("quasi") delay-insensitive cell based on the "half-buffering" techniques developed by Lines and Martin at Caltech. The cells are able to cycle at speeds approaching full-custom logic in the same process technology, and it is possible to use a pipelined communications network to allow such speeds to be attained in the communications network as well.
Potential Applications
- Times faster embedded logic array (from under 100MHz improves up to 2GHz).
- Embedded FPGA becomes possible to match operating speeds of a nanometer SoC.
- Lower Power Pipeline achievements can be used in high complexity processors.
Inventor Team
A joint team led by Prof Chen Hongyi & Prof Chen Hong of Tsinghua University, Mika Nyström, PhD of Caltech.
Academic Citations
US ARVLSI (1997)
FTC
Business Development and China partnership development.
行业背景
大规模现场可编程逻辑器件的性能改进，理论上可取决于在其阵列单元的可编程逻辑中使用强化的流水管线电路结构：例如栓索所有的查找表(LUT)。但一般来说这样的做法又被其他因素所制约：
- 增加延迟，如LUT的操作如此将需要整个时钟周期；
- 由于每个逻辑栓索的操作即使在没有逻辑值变化时仍要消耗电能，功耗太大。
技术发明
建议使用"自主时钟的流水管线FPGA体系结构，形成不受延迟影响的"半缓存"电路（发明人加州理工学院Lines和Martin）。如此的FPGA阵列单元可以达到与全定制逻辑电路类比的速度。同此，流水管线的通讯网络可以使这样的高速逻辑在阵列单元间达到同速的高效通讯。
应用方向
- 10倍以上提速的现场可编程逻辑阵列器件（从通常的百兆赫兹以下到千兆赫兹以上）。
- 由于可达到与正常逻辑电路同等的速度，进入单芯片系统嵌入式FPGA成为实用可能。
- 低功耗流水管线体系结构终于可能用于改进高复杂微处理器的性能。
发明人
Mika Nyström | 博士
容思锐智
首席顾问陈弘毅
学术认可
美国ARVLSI(1997)等
